A DRAM cell typically includes a MOS transistor and a capacitor. An example of such a DRAM cell is shown in FIG. 1. The DRAM cell 10 of FIG. 1 has a MOSFET 12 and a capacitor 14. A word line is connected to the gate of the MOSFET 12. A bit line is connected to the source of the MOSFET 12. The capacitor 14 is connected to the drain of the MOSFET 12. The logic state of the DRAM cell is determined by whether or not the capacitor 14 is holding a charge.
The DRAM cell 10 is read by using the bit line to determine whether or not a charge is stored in the capacitor 14. The DRAM cell 10 is written by using the bit line to add or remove charge from the capacitor 14. However, the cell can only be read or written when the cell 10 is addressed (i.e., activated) by the word line.
It is an object of the present invention to provide a higher capacitance for each DRAM cell.